Memory elements are necessary constituent parts of digital systems alongside the logic circuits. A distinction is made between RAM memories, which enable both write and read accesses, and ROM memories, in which only read accesses are possible. RAM memories can be subdivided into static RAMs (SRAM), in which the memory function is realized by a flip-flop or a bistable circuit with nonlinear feedback, and dynamic RAMs (DRAM) in which the information is stored as a quantity of charge on a capacitor.
FIG. 1 shows a detail having four memory elements SE from the cell array of an SRAM. A memory element SE is required for each bit, the memory element comprising two feedback inverters I. The memory elements SE are each connected to a horizontally running word line WL and two vertically running bit lines BL1 and BL2. A row of memory elements SE can be selected by a word line potential VWL being applied to one of the word lines WL. The memory elements SE of the selected row are linked to the corresponding bit lines BL1 and BL2 via selection transistors T, the control inputs of which are driven by the word line WL. For reading the content of a memory element SE, a sense amplifier is connected to the bit lines BL1 and BL2, while for writing purposes the bit lines BL1 and BL2 are connected to a driver. The use of complementary levels at the bit lines BL1 and BL2 makes it possible to increase the reliability and reduce the sensitivity to fluctuations in the component sizes. The bit lines BL1 and BL2 can be precharged to a precharge potential VP in a precharge unit VE by means of precharge transistors TV. For this purpose, a precharge signal PC having a high level must be present at the control inputs of the precharge transistors TV. The read and write operations can be shortened as a result of the precharging of the bit lines BL1 and BL2. At a precharge potential VP=VDD/2, where VDD is the supply potential, only a voltage swing of VDD/2 occurs upon charge reversal to VDD or GND at each bit line BL1 and BL2, whereby the quantity of charge that is to be subjected to charge reversal and thus the required time are reduced.
SRAM memories are also used in the integrated circuits arranged in smart cards. The information stored in the smart cards, which is generally not freely accessible, serves for authorization and identification, for example when managing an account. It is not surprising, therefore, that smart cards are subject to attacks with the intention of covertly observing this information. One of the most important methods of attack is differential power analysis (DPA). In the course of a DPA, the current consumption of a smart card is measured over one or more clock cycles, a model is created and statistical methods are used in an attempt to draw conclusions about the stored information from the correlation of systematic data variations and current consumption.
Since smart cards have small dimensions, conventional defense measures against DPA, such as, for example, shielding and large capacitors which minimize variations in the current consumption, cannot be employed. For protection against a DPA, therefore, recourse is had to so-called dual rail precharged circuit technology. Dual rail means that each node in the circuit is assigned a second node having a complementary level with respect to the level of the first node. Signals are simultaneously transmitted and processed on both nodes. The logic value 0 is assigned the complementary value 1 and the pair (0, 1) is obtained; the value 1 is assigned the complementary value 0 and the pair (1, 0) is obtained. If the data paths for both nodes are embodied physically identically, then it is no longer possible to identify by means of a DPA whether a 1 or a 0 has been transmitted or processed, since the complementary value has been concomitantly transmitted in both cases. Thus, independently of the level or state, exactly a 1 and a 0 are always transmitted or processed.
For protection against a DPA, it must also not be possible to be able to distinguish the four possible transitions of the signal states 0→0, 0→1, 1→0, 1→1 on the basis of the current consumption. If a state does not change, as for example in the case of the transitions 0→0 and 1→1, no current would flow in the case of a CMOS realization, but current would flow in the case of the transitions 0→1 and 1→0. In order that all transitions have the same current consumption, a so-called precharge state is inserted prior to each transition. In the precharge state, the node and its assigned node have the same levels. Depending on whether a precharge to high or low is effected, the logically invalid intermediate states (1, 1) or (0, 0) arise. In each of the four possible transitions, as a result of the precharge, only exactly one of the nodes is charged and the other node is discharged. Therefore, the transitions can no longer be distinguished on the basis of their current consumption and are consequently safeguarded against a DPA.
Conventional SRAM cells are already designed using dual rail precharged circuit technology for design-related reasons in the case of read accesses. The first storage node X and the second storage node Y in each memory element SE have mutually complementary levels. Independently of the value stored in the memory element SE, one of the storage nodes X or Y always has a low level and the other a high level, which is also evident from the fact that the storage nodes X and Y are in each case connected to one another via an inverter I.
The first bit line BL1 and the second bit line BL2 also have mutually complementary levels if they are not actually precharged to the precharge potential VP by the precharge transistors TV. In the event of reading the memory elements SE, the first bit line BL1 and the second bit line BL2 are connected to the first storage node X and the second storage node Y, respectively, by the selection transistors T. The mutually complementary levels at the first storage node X and the second storage node Y are thus forwarded to the first bit line BL1 and the second bit line BL2, so that these also have mutually complementary levels.
Between the read accesses, the first bit line BL1 and the second bit line BL2 are precharged to the potential VP=VDD/2 by the precharge unit VE. It will now be assumed that a high level corresponds to the supply potential VDD and a low level corresponds to the ground potential GND=0 V. If the first storage node X has a high level and the second storage node Y has a low level, then during reading the first bit line BL1 is charged from VDD/2 to VDD, which means a voltage change of +VDD/2. At the same time, the second bit line BL2 is discharged from VDD/2 to 0 volts, which represents a voltage difference of −VDD/2. Given an identical physical realization of the first bit line BL1 and of the second bit line BL2, the same quantity of charge in each case flows for charging and discharging, so that overall a vanishing charge integral results. If, by contrast, the first storage node X has a low level and the second storage node Y has a high level, then the polarities of the voltage swings are interchanged, but the charge integral is zero again. During reading, therefore, it is not possible to ascertain whether a high level or a low level is stored or read out. Therefore, the stored information cannot be analyzed by means of current profiles, so that a conventional SRAM cell is already safeguarded against a DPA during reading.
When writing to a conventional SRAM cell, the first bit line BL1 and the second bit line BL2 to which the memory element SE to be read is connected are selected and connected to a bit line driver. In this case, the first bit line BL1 has a complementary level with respect to the second bit line BL2. If a word line potential VWL is applied to the word line WL which is connected to the control inputs of the selection transistors T of the memory element SE to be written to, then the first storage node X is connected to the first bit line BL1 and the second storage node Y is connected to the second bit line BL2. The first storage node X and the second storage node Y then likewise have mutually complementary levels.
In contrast to the read operation, during writing the charge integral depends on the state stored in the memory element SE and the state to be written. If the first storage node X and the second storage node Y already have the potentials of the first bit line BL1 and the second bit line BL2, then no shunt current flows through the memory element SE. However, if the level of the storage nodes X and Y is to be changed by application of corresponding levels to the first bit line BL1 and the second bit line BL2, then a shunt current flows through the memory element SE as a result of a simultaneous change in the levels of the storage nodes X and Y. The shunt current is particularly pronounced if the inverters I are embodied using CMOS technology. Since different currents flow depending on the stored value and the value to be written, it is possible, in principle, to specify a relationship concerning the memory content and the data to be written on the basis of an analysis of the current profile.